Chip selection or addressing in memories generally requires selecting a particular chip from an array of many. To do this usually requires that each chip in a bank or array of chips have a set of chip selects that respond to a unique address from a memory controller of some kind.
Since memory chips are usually identical and chip enable signals are permanently hard wired (e.g., active-high or active-low) a chip requires a large number of chip selects in order to respond to a unique address. Normally, the number of chip selects is equal to the number of times the chip count is doubled in an array of chips, plus one. This can be expressed as (2n+1), where ‘n’ is the number of times the chip count has been doubled, i.e., where the chip count equals 2n. This scheme limits the number of chips that can be effectively accommodated by a given number of chip selects in a memory device.
Currently, synchronous SRAMs include 2 or more chip select pins, which enable a user to activate or de-activate the device, thereby allowing access to the memory within the device. The chip select pins are also used when interfacing the SRAMs in a system, where the memory size needs to be increased. These pins allow the system to turn on one part of the memory (SRAM chip) while turning off the other part of the memory.
Conventional art FIG. 1 shows an example of how four SRAMs are used for enabling access of a memory size four times the size of each memory device. Each device has identical chip select assertion levels. As shown, 5 chip selects are needed for this type of interface. One of the chip selects is used to control the whole bank and the rest to control each of the devices independently. It can be seen that two of the chip selects in each of the devices are not utilized and are permanently grounded or powered up to the supply voltage. The reason for this is because all of the chip selects are alike in each SRAM and four combinations of chip selects are needed to select one of the SRAMs.
Conventional art FIG. 1 illustrates an implementation of this existing memory selection scheme. Each memory chip 101 to 104 is implemented with five chip selects, CE1 through CE5. In each chip, chip selects CE2 and CE4 are active high, and ship selects /CE1, /CE3, and /CE5 are active low, as indicated by the leading “/”. Vdd is always high and is connected to one or two pins in three of the four illustrated chips. Ground is also connected to one or two pins in three of the four chips. Memory controller 110 is capable of outputting three high or low chip select signals, and thus is capable of writing a three bit word of “000”, “001”, “010”, or “011” to access chips 101 through 104, respectively, where /CE1 selects the entire bank.
The extra chip selects not used by the controller are coupled to a “high” or to a ground, therefore each chip must have five chip selects in order to be able to address four chips. Addressing eight chips requires six chips selects and so on, in accord with the above expression (2n+1).
To formalize the conventional art generally, (2n+1) chip selects are needed on each of the SRAMs for effective expanding of the memory 2n times, where ‘n’ is the number of times the memory needs to be doubled in a compounded fashion or, expressed differently, where the number of selectable chips is equal to 2n. The extra chip select for which ‘1’ accounts is generally used for selecting or de-selecting the entire bank or array of chips.